Low-Power Design of Nanometer FPGAs: Architecture and EDA

Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.

Low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesignComprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipationProvides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques

Chapter 1: FPGA Overview: Architecture and CAD Chapter 2: Power Dissipation in Modern FPGAs Chapter 3: Power Estimation in FPGAs Chapter 4: Dynamic Power Reduction Techniques in FPGAs Chapter 5: Leakage Power Reduction in FPGAs Using MTCMOS Techniques Chapter 6: Leakage Power Reduction in FPGAs Through Input Pin Reordering