Handbook of 3D Integration, Volume 3: 3D Process Technology

Edited by key figures in 3D integration and written by top authors from high–tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large–scale implementation of this emerging technology. Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

List of Contributors XVII 1 3D IC Integration Since 2008 1 Philip Garrou, Peter Ramm, and Mitsumasa Koyanagi 1.1 3D IC Nomenclature 1 1.2 Process Standardization 2 1.3 The Introduction of Interposers (2.5D) 4 1.4 The Foundries 6 1.4.1 TSMC 6 1.4.2 UMC 7 1.4.3 Global Foundries 7 1.5 Memory 7 1.5.1 Samsung 7 1.5.2 Micron 8 1.5.3 Hynix 9 1.6 The Assembly and Test Houses 9 1.7 3D IC Application Roadmaps 10 References 11 2 Key Applications and Market Trends for 3D Integration and Interposer Technologies 13 Rozalia Beica, Jean–Christophe Eloy, and Peter Ramm 2.1 Introduction 13 2.2 Advanced Packaging Importance in the Semiconductor Industry is Growing 16 2.3 3D Integration–Focused Activities – The Global IP Landscape 18 2.4 Applications, Technology, and Market Trends 22 References 32 3 Economic Drivers and Impediments for 2.5D/3D Integration 33 Philip Garrou 3.1 3D Performance Advantages 33 3.2 The Economics of Scaling 33 3.3 The Cost of Future Scaling 34 3.4 Cost Remains the Impediment to 2.5D and 3D Product Introduction 37 3.4.1 Required Economics for Interposer Use in Mobile Products 38 3.4.2 Silicon Interposer Pricing 38 References 40 4 Interposer Technology 41 Venky Sundaram and Rao R. Tummala 4.1 Definition of 2.5D Interposers 41 4.2 Interposer Drivers and Need 42 4.3 Comparison of Interposer Materials 44 4.4 Silicon Interposers with TSV 45 4.5 Lower Cost Interposers 48 4.5.1 Glass Interposers 48 4.5.2 Low–CTE Organic Interposers 53 4.5.3 Polycrystalline Silicon Interposer 55 4.6 Interposer Technical and Manufacturing Challenges 57 4.7 Interposer Application Examples 58 4.8 Conclusions 60 References 61 5 TSV Formation Overview 65 Dean Malta 5.1 Introduction 65 5.2 TSV Process Approaches 67 5.2.1 TSV–Middle Approach 68 5.2.2 Backside TSV–Last Approach 68 5.2.3 Front–Side TSV–Last Approach 69 5.3 TSV Fabrication Steps 70 5.3.1 TSV Etching 70 5.3.2 TSV Insulation 71 5.3.3 TSV Metallization 71 5.3.4 Overburden Removal by CMP 72 5.3.5 TSV Anneal 73 5.3.6 Temporary Carrier Wafer Bonding and Debonding 74 5.3.7 Wafer Thinning and TSV Reveal 74 5.4 Yield and Reliability 75 References 76 6 TSV Unit Processes and Integration 79 Sesh Ramaswami 6.1 Introduction 79 6.2 TSV Process Overview 80 6.3 TSV Unit Processes 82 6.3.1 Etching 82 6.3.2 Insulator Deposition with CVD 83 6.3.3 Metal Liner/Barrier Deposition with PVD 84 6.3.4 Via Filling by ECD of Copper 84 6.3.5 CMP of Copper 85 6.3.6 Temporary Bonding between Carrier and Device Wafer 86 6.3.7 Wafer Backside Thinning 86 6.3.8 Backside RDL 87 6.3.9 Metrology, Inspection, and Defect Review 87 6.4 Integration and Co–optimization of Unit Processes in Via Formation Sequence 88 6.5 Co–optimization of Unit Processes in Backside Processing and Via–Reveal Flow 89 6.6 Integration and Co–optimization of Unit Processes in Via–Last Flow 91 6.7 Integration with Packaging 92 6.8 Electrical Characterization of TSVs 92 6.9 Conclusions 96 References 97 7 TSV Formation at ASET 99 Hiroaki Ikeda 7.1 Introduction 99 7.2 Via–Last TSV for Both D2D and W2W Processes in ASET 103 7.3 TSV Process for D2D 105 7.3.1 Front–Side Bump Forming 106 7.3.2 Attach WSS and Thinning 106 7.3.3 Deep Si Etching from the Backside 107 7.3.4 Liner Deposition 107 7.3.5 Removal of SiO2 at the Bottom of Via 107 7.3.6 Barrier Metal and Seed Layer Deposition by PVD 110 7.3.7 Cu Electroplating 110 7.3.8 CMP 110 7.3.9 Backside Bump 111 7.3.10 Detach WSS 111 7.3.11 Dicing 112 7.4 TSV Process for W2W 113 7.4.1 Polymer Layer Coat and Development 114 7.4.2 Barrier Metal and Seed Layer Deposition 114 7.4.3 Cu Plating 114 7.4.4 CMP 115 7.4.5 First W2W Stacking (Face to Face) 116 7.4.6 Wafer Thinning and Deep Si Etching 116 7.4.7 TSV Liner Deposition and SiO2 Etching of Via Bottom 117 7.4.8 Barrier Metal and Seed Layer Deposition and Cu Plating 117 7.4.9 CMP 117 7.4.10 Next W2W Stacking 118 7.5 Conclusions 119 References 119 8 Laser–Assisted Wafer Processing: New Perspectives in Through–Substrate Via Drilling and Redistribution Layer Deposition 121 Marc B. Hoppenbrouwers, Gerrit Oosterhuis, Guido Knippels, and Fred Roozeboom 8.1 Introduction 121 8.2 Laser Drilling of TSVs 121 8.2.1 Cost of Ownership Comparison 121 8.2.2 Requirements for an Industrial TSV Laser Driller 123 8.2.3 Drilling Strategy 124 8.2.4 Experimental Drilling Results 126 8.3 Direct–Write Deposition of Redistribution Layers 126 8.3.1 Introduction on Redistribution Layers 126 8.3.2 Direct–Write Characteristics 127 8.3.3 Direct–Write Laser–Induced Forward Transfer 128 8.3.4 LIFT Results 130 8.4 Conclusions and Outlook 131 References 132 9 Temporary Bonding Material Requirements 135 Rama Puligadda 9.1 Introduction 135 9.2 Technology Options 136 9.2.1 Tapes and Waxes 136 9.2.2 Chemical Debonding 136 9.2.3 Thermoplastic Bonding Material and Slide Debonding 136 9.2.4 Debonding Using Release Layers 137 9.3 Requirements of a Temporary Bonding Material 138 9.4 Considerations for Successful Processing 139 9.4.1 Application of the Temporary Bonding Adhesive to the Device Wafer and Bonding to Carrier 139 9.4.2 Moisture and Contaminants on Surface 139 9.4.3 Total Thickness Variation 140 9.4.4 Squeeze Out 140 9.5 Surviving the Backside Process 141 9.5.1 Edge Trimming 142 9.5.2 Edge Cleaning 142 9.5.3 Temperature Excursions in Plasma Processes 143 9.5.4 Wafer Warpage due to CTE Mismatch 143 9.6 Debonding 144 9.6.1 Debonding Parameters in Slide–Off Debonding 144 9.6.2 Mechanical Damage to Interconnects 144 References 145 10 Temporary Bonding and Debonding – An Update on Materials and Methods 147 Wilfried Bair 10.1 Introduction 147 10.2 Carrier Selection for Temporary Bonding 148 10.3 Selection of Temporary Bonding Adhesives 151 10.4 Bonding and Debonding Processes 152 10.5 Equipment and Process Integration 155 References 156 11 ZoneBOND1: Recent Developments in Temporary Bonding and Room–Temperature Debonding 159 Thorsten Matthias, J€urgen Burggraf, Daniel Burgstaller, Markus Wimplinger, and Paul Lindner 11.1 Introduction 159 11.2 Thin Wafer Processing 159 11.2.1 Thin Wafer Total Thickness Variation 161 11.2.2 Wafer Alignment 163 11.3 ZoneBOND Room–Temperature Debonding 163 11.4 Conclusions 165 References 166 12 Temporary Bonding and Debonding at TOK 167 Shoji Otaka 12.1 Introduction 167 12.2 Zero Newton Technology 168 12.2.1 The Wafer Bonder 168 12.2.2 The Wafer Debonder 170 12.2.3 The Wafer Bonder and Debonder Equipment Lineups 170 12.2.4 Adhesives 170 12.2.5 Integration Process Performance 172 12.3 Conclusions 174 References 174 13 The 3MTM Wafer Support System (WSS) 175 Blake Dronen and Richard Webb 13.1 Introduction 175 13.2 System Description 175 13.3 General Advantages 177 13.4 High–Temperature Material Solutions 178 13.5 Process Considerations 180 13.5.1 Wafer and Adhesive Delamination 180 13.5.2 LTHC Glass Delamination 181 13.6 Future Directions 181 13.6.1 Thermal Stability 181 13.6.2 Elimination of Adhesion Control Agents 182 13.6.3 Laser–Free Release Layer 183 13.7 Summary 183 Reference 184 14 Comparison of Temporary Bonding and Debonding Process Flows 185 Matthew Lueck 14.1 Introduction 185 14.2 Studies of Wafer Bonding and Thinning 186 14.3 Backside Processing 186 14.4 Debonding and Cleaning 188 References 189 15 Thinning, Via Reveal, and Backside Processing – Overview 191 Eric Beyne, Anne Jourdain, and Alain Phommahaxay 15.1 Introduction 191 15.2 Wafer Edge Trimming 192 15.3 Thin Wafer Support Systems 194 15.3.1 Glass Carrier Support System with Laser Debonding Approach 196 15.3.2 Thermoplastic Glue Thin Wafer Support System – Thermal Slide Debondable System 196 15.3.3 Room–Temperature, Peel–Debondable Thin Wafer Support Systems 197 15.4 Wafer Thinning 198 15.5 Thin Wafer Backside Processing 202 15.5.1 Via–Middle Thin Wafer Backside Processing: “Via–Reveal” Process 202 15.5.2 Via–Last Thin Wafer Backside Processing 203 References 205 16 Backside Thinning and Stress–Relief Techniques for Thin Silicon Wafers 207 Christof Landesberger, Christoph Paschke, Hans–Peter Sp€ohrle, and Karlheinz Bock 16.1 Introduction 207 16.2 Thin Semiconductor Devices 207 16.3 Wafer Thinning Techniques 208 16.3.1 Wafer Grinding 209 16.3.2 Wet–Chemical Spin Etching 210 16.3.3 CMP Polishing 211 16.3.4 Plasma Dry Etching 212 16.3.5 Dry Polish 213 16.3.6 Chemical–Mechanical Grinding (CMG) 214 16.4 Fracture Tests for Thin Silicon Wafers 214 16.5 Comparison of Stress–Relief Techniques for Wafer Backside Thinning 216 16.6 Process Flow for Wafer Thinning and Dicing 220 16.7 Summary and Outlook on 3D Integration 222 References 223 17 Via Reveal and Backside Processing 227 Mitsumasa Koyanagi and Tetsu Tanaka 17.1 Introduction 227 17.2 Via Reveal and Backside Processing in Via–Middle Process 227 17.3 Backside Processing in Back–Via Process 232 17.4 Backside Processing and Impurity Gettering 234 17.5 Backside Processing for RDL Formation 237 References 239 18 Dicing, Grinding, and Polishing (Kiru Kezuru and Migaku) 241 Akihito Kawai 18.1 Introduction 241 18.2 Grinding and Polishing 241 18.2.1 Grinding General 241 18.2.2 Thinning 243 18.2.3 Grinding Topics for 3DIC Such as TSV Devices 246 18.3 Dicing 250 18.3.1 Blade Dicing General 250 18.3.2 Thin Wafer Dicing 253 18.3.3 Low–k Dicing 254 18.3.4 Other Laser Dicing 254 18.3.5 Dicing Topics for 3D–IC Such as TSV 257 18.4 Summary 260 Further Reading 260 19 Overview of Bonding and Assembly for 3D Integration 261 James J.–Q. Lu, Dingyou Zhang, and Peter Ramm 19.1 Introduction 261 19.2 Direct, Indirect, and Hybrid Bonding 262 19.3 Requirements for Bonding Process and Materials 263 19.4 Bonding Quality Characterization 267 19.5 Discussion of Specific Bonding and Assembly Technologies 269 19.6 Summary and Conclusions 273 References 274 20 Bonding and Assembly at TSMC 279 Douglas C.H. Yu 20.1 Introduction 279 20.2 Process Flow 280 20.3 Chip–on–Wafer Stacking 281 20.4 CoW–on–Substrate (CoWoS) Stacking 283 20.5 CoWoS Versus CoCoS 283 20.6 Testing and Known Good Stacks (KGS) 284 20.7 Future Perspectives 285 References 285 21 TSV Packaging Development at STATS ChipPAC 287 Rajendra D. Pendse 21.1 Introduction 287 21.2 Development of the 3DTSV Solution for Mobile Platforms 289 21.3 Alternative Approaches and Future Developments 293 References 294 22 Cu–SiO2 Hybrid Bonding 295 Léa Di Cioccio, S. Moreau, Loïc Sanchez, Floriane Baudin, Pierric Gueguen, Sebastien Mermoz, Yann Beilliard, and Rachid Taibi 22.1 Introduction 295 22.2 Blanket Cu–SiO2 Direct Bonding Principle 296 22.2.1 Chemical–Mechanical Polishing Parameters 296 22.3 Aligned Bonding 299 22.3.1 Wafer–to–Wafer Bonding 299 22.3.2 Die–to–Wafer Bonding in Pick–and–Place Equipment 299 22.3.3 Die–to–Wafer by the Self–Assembly Technique 300 22.4 Blanket Metal Direct Bonding Principle 302 22.5 Electrical Characterization 304 22.5.1 Wafer–to–Wafer and Die–to–Wafer Copper–Bonding Electrical Characterization 304 22.5.2 Reliability 307 22.5.3 Thermal Cycling 307 22.5.4 Stress Voiding (SIV) Test on 200 —C Postbonding Annealed Samples 308 22.5.5 Package–Level Electromigration Test 309 22.6 Conclusions 310 References 311 23 Bump Interconnect for 2.5D and 3D Integration 313 Alan Huffman 23.1 History 313 23.2 C4 Solder Bumps 315 23.3 Copper Pillar Bumps 316 23.4 Cu Bumps 319 23.5 Electromigration 320 References 322 24 Self–Assembly Based 3D and Heterointegration 325 Takafumi Fukushima and Jicheol Bea 24.1 Introduction 325 24.2 Self–Assembly Process 325 24.3 Key Parameters of Self–Assembly on Alignment Accuracies 327 24.4 How to Interconnect Self–Assembled Chips to Chips or Wafers 328 24.4.1 Flip–Chip–to–Wafer 3D Integration 329 24.4.2 Reconfigured–Wafer–to–Wafer 3D Integration 331 References 332 25 High–Accuracy Self–Alignment of Thin Silicon Dies on Plasma–Programmed Surfaces 335 Christof Landesberger, Mitsuru Hiroshima, Josef Weber, and Karlheinz Bock 25.1 Introduction 335 25.2 Principle of Fluidic Self–Alignment Process for Thin Dies 335 25.3 Plasma Programming of the Surface 336 25.4 Preparation of Materials for Self–Alignment Experiments 337 25.5 Self–Alignment Experiments 338 25.6 Results of Self–Alignment Experiments 339 25.7 Discussion 341 25.8 Conclusions 342 References 343 26 Challenges in 3D Fabrication 345 Douglas C.H. Yu 26.1 Introduction 345 26.2 High–Volume Manufacturing for 3D Integration 346 26.3 Technology Challenges 346 26.4 Front–Side and Backside Wafer Processes 346 26.5 Bonding and Underfills 350 26.6 Multitier Stacking 352 26.7 Wafer Thinning and Thin Die and Wafer Handling 353 26.8 Strata Packaging and Assembly 356 26.9 Yield Management 359 26.10 Reliability 360 26.11 Cost Management 362 26.12 Future Perspectives 362 References 364 27 Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices 365 Eric Beyne, Joke De Messemaeker, and Wei Guo 27.1 Introduction 365 27.2 Cu Stress in TSV 365 27.3 Mitigation of Cu Pumping 368 27.4 Impact of TSVs on FEOL Devices 371 References 378 28 Implications of Stress/Strain and Metal Contamination on Thinned Die 379 Kangwook Lee and Mariappan Murugesan 28.1 Introduction 379 28.2 Impacts of Cu Contamination on Device Reliabilities in Thinned 3DLSI 379 28.3 Impacts of Local Stress and Strain on Device Reliabilities in Thinned 3DLSI 386 28.3.1 Microbump–Induced Stresses in Stacked LSIs 387 28.3.2 Microbump–Induced TMS in LSI 388 28.3.3 Microbump–Induced LMS 389 References 391 29 Metrology Needs for 2.5D/3D Interconnects 393 Victor H. Vartanian, Richard A. Allen, Larry Smith, Klaus Hummler, Steve Olson, and Brian Sapp 29.1 Introduction: 2.5D and 3D Reference Flows 393 29.2 TSV Formation 394 29.2.1 TSV Etch Metrology 395 29.2.2 Liner, Barrier, and Seed Metrology 397 29.2.3 Copper Fill Metrology (TSV Voids) 399 29.2.4 Cross–Sectional SEM (Focused Ion Beam Milling Sample Preparation) 400 29.2.5 X–Ray Microscopy and CT Inspection 400 29.2.6 Stress Metrology in Cu and Si 402 29.3 MEOL Metrology 404 29.3.1 Edge Trim Inspection 405 29.3.2 Bond Voids and Bond Strength Metrology 406 29.3.3 Bond Strength Metrology 409 29.3.4 Bonded Wafer Thickness, Bow, and Warp 410 29.3.5 TSV Reveal Metrology 418 29.4 Assembly and Packaging Metrology 420 29.4.1 Wafer–Level C4 Bump and Microbump Metrology and Inspection 421 29.4.2 Package–Level Inspection: Scanning Acoustic Microscopy 422 29.4.3 Package–Level Inspection: X–Rays 424 29.5 Summary 426 References 427 Index 431

Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Dir. of Technology and Business Dev. for Dow Chemicals′ Electronic Materials business. Dr. Garrou is a Fellow of IEEE and IMAPS and served as President of the IEEE CPMT Society and IMAPS. He has co–authored 3 microelectronics texts and 100+ publications. He is Assoc. Ed. and author of the weekly blog "Insights from the Leading Edge" for Solid State Technology and has co–authored 3DIC reports for both TechSearch and Yole. Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three–year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the Solid–State Devices and Materials Award. Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for the key competence "Si Processes, Device and 3D Integration". He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is co–author of over 100 publications and 24 patents and editor of Wiley′s "Handbook of Wafer Bonding". He received the "Ashman Award 2009" from IMAPS "For Pioneering Work on 3D IC Stacking and Integration".