RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

The skills and guidance needed to master RTL hardware design
This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module–level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module–level design and can be synthesized into efficient gate–level implementation.
Several unique features distinguish the book:Coding style that shows a clear relationship between VHDL constructs and hardware componentsConceptual diagrams that illustrate the realization of VHDL codesEmphasis on the code reusePractical examples that demonstrate and reinforce design concepts, procedures, and techniquesTwo chapters on realizing sequential algorithms in hardwareTwo chapters on scalable and parameterized designs and codingOne chapter covering the synchronization and interface between multiple clock domains
Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices.
With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper–level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today′s synthesis software and FPGA devices should also refer to this book.

Spis treści:
Preface.
Acknowlegmentss.
1. Introduction to Digital System Design.
2. Overview on Hardware Description Language.
3. Basic Language Constructs of VHDL.
4. Concurrent Signal Assignment Statements of VHDL.
5. Sequential Statements of VHDL.
6. Synthesis of VHDL Code.
7. Combinational Circuit Design: Practice.
8. Sequential Circuit Design: Principle.
9. Sequential Circuit Design: Practice.
10. Finite State Machine: Princple and Practice.
11. Register Transfer Methodology: Principle.
12. Register Transfer Methodology: Practice.
13. Hierarchical Design in VHDL.
14. Parameterized Design: Principle.
15. Parameterized Design: Practice.
16. Clock and Synchronization: Principle and Practice.
References.
Index.

Nota biograficzna:
PONG P. CHU, PhD, is Associate Professor in the Department of Electrical and Computer Engineering, Cleveland State University. He has received grants from both NASA and the National Science Foundation, and has taught undergraduate and graduate–level digital systems and computer architecture courses for more than a decade.


Okładka tylna:
The skills and guidance needed to master RTL hardware design
This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module–level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module–level design and can be synthesized into efficient gate–level implementation.
Several unique features distinguish the book:Coding style that shows a clear relationship between VHDL constructs and hardw are componentsConceptual diagrams that illustrate the realization of VHDL codesEmphasis on the code reusePractical examples that demonstrate and reinforce design concepts, procedures, and techniquesTwo chapters on realizing sequential algorithms in hardwareTwo chapters on scalable and parameterized designs and codingOne chapter covering the synchronization and interface between multiple clock domains
Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices.
With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper–level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today′s synthesis software and FPGA devices should also refer to this book.