High Level Synthesis of Pipelined Datapaths

The pipelined mode of data processing has been developed in response to the growing complexity and increased speed requirement of ASICs (application specific integrated circuits). Providing an insight into the High Level Synthesis (HLS) algorithms used for the pipelined datapaths of hardware components, the book illustrates these methodologies in hardware/software co–design and system level synthesis.
Features include:
∗ The unique CAD tool, PIPE, which performs and illustrates all the basic HLS steps suited to work on pipelined datapath designs.
∗ Accompanying CD ROM featuring a step–by–step PIPE tutorial, yielding an allocated structural description of the pipelined datapath.
∗ Models and methods for solving HLS problems, including illustration of the applications potential, advantages, drawbacks and benchmark results of PIPE.
∗ Descriptions of the relevant control principles and the unique handling of multiple–process recursive loops.
∗ Thorough coverage of the basic algorithms for data dominated structures, such as scheduling, allocation, buffer insertion, replication of operations and synchronisation.
This accessible guide to high level synthesis will appeal to advanced students in electrical engineering and computer science. Hardware engineers and designers using pipelined datapaths and logic synthesis will also find this an indispensable aid.

Spis treści:
Preface.
Introduction.
The Elementary Operation Graph (EOG).
Reducing the Restarting Period.
Synchronization.
Examples for Applying the Algorithms RESTART and SYNC.
Scheduling as Arrangement of Synchronizing Delay Effects.
Allocation.
Combinatorial and Asynchronous Operations.
Multiple–Process Recursive Loops.
Control Principles.
Scheduling Methods.
Examples for Comparison of the Scheduling Algorithms.
The Design Tool PIPE.
Effective Graph Generation.
SystemR 11;Level Synthesis Principles.
Solved Problems.
Further Reading.
Glossary.
References.
Index.

Okładka tylna:
The pipelined mode of data processing has been developed in response to the growing complexity and increased speed requirement of ASICs (application specific integrated circuits). Providing an insight into the High Level Synthesis (HLS) algorithms used for the pipelined datapaths of hardware components, the book illustrates these methodologies in hardware/software co–design and system level synthesis.
Features include:
∗ The unique CAD tool, PIPE, which performs and illustrates all the basic HLS steps suited to work on pipelined datapath designs.
∗ Accompanying CD ROM featuring a step–by–step PIPE tutorial, yielding an allocated structural description of the pipelined datapath.
∗ Models and methods for solving HLS problems, including illustration of the applications potential, advantages, drawbacks and benchmark results of PIPE.
∗ Descriptions of the relevant control principles and the unique handling of multiple–process recursive loops.
∗ Thorough coverage of the basic algorithms for data dominated structures, such as scheduling, allocation, buffer insertion, replication of operations and synchronisation.
This accessible guide to high level synthesis will appeal to advanced students in electrical engineering and computer science. Hardware engineers and designers using pipelined datapaths and logic synthesis will also find this an indispensable aid.