Design for Embedded Image Processing on FPGAs

Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine–grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned.Provides a bridge between algorithms and hardwareDemonstrates how to avoid many of the potential pitfallsOffers practical recommendations and solutionsIllustrates several real–world applications and case studiesAllows those with software backgrounds to understand efficient hardware implementation
Design for Embedded Image Processing on FPGAs is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.
The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.
Lecture slides for instructors available at:
www.wiley.com/go/bailey/fpga

Spis treści:
Preface.
Acknowledgements.
1 Image Processing.
1.1 Basic Definitions.
1.2 Image Formation.
1.3 Image Processing Operations.
1.4 Example Application.
1.5 Real–Time Image Processing.
1.6 Embedded Image Processing.
1.7 Serial Processing.
1.8 Parallelism.
1.9 Hardware Image Processing Systems.
2 Field Programmable Gate Arrays.
2.1 Programmable Logic.
2.2 FPGAs and Image Processing.
2.3 Inside an FPGA.
2.4 FPGA Families and Features.
2.5 Choosing an FPGA or Development Board.
3 Languages.
3.1 Hardware Description Languages.
3.2 Software–Based Languages.
3.3 Visual Languages.
3.4 Summary.
4 Design Process.
4.1 Problem Specification.
4.2 Algorithm Development.
4.3 Architecture Selection.
4.4 System Implementation.
4.5 Designing for Tuning and Debugging.
5 Mapping Techniques.
5.1 Timing Constraints.
5.2 Memory Bandwidth Constraints.
5.3 Resource Constraints.
5.4 Computational Techniques.
5.5 Summary.
6 Point Operations.
6.1 Point Operations on a Single Image.
6.2 Point Operations on Multiple Images.
6.3 Colour Image Processing.
6.4 Summary.
7 Histogram Operations.
7.1 Greyscale Histogram.
7.2 Multidimensional Histograms.
8 Local Filters.
8.1 Caching.
8.2 Linear Filters.
8.3 Nonlinear Filters.
8.4 Rank Filters .
8.5 Colour Filters.
8.6 Morphological Filters.
8.7 Adaptive Thresholding.
8.8 Summary.
9 Geometric Transformations.
9.1 Forward Mapping.
9.2 Reverse Mapping.
9.3 Interpolation.
9.4 Mapping Optimisations.
9.5 Image Registration.
10 Linear Transforms.
10.1 Fourier Transform.
10.2 Discrete Cosine Transform.
10.3 Wavelet Transform.
10.4 Image and Video Coding.
11 Blob Detection and Labelling.
11.1 Bounding Box.
11.2 Run–Length Coding.
11.3 Chain Coding.
11.4 Connected Component Labelling.
11.5 Distance Transform.
11.6 Watershed Transform.
11.7 Hough Transform.
11.8 Summary.
12 Interfacing.
12.1 Camera Input.
12.2 Display Output.
12.3 Serial Communication.
12.4 Memory.
12.5 Summary.
13 Testing, Tuning and Debugging.
13.1 Design.
13.2 Implementation.
13.3 Tuning.
13.4 Timing Closure.
14 Example Applications.
14.1 Coloured Region Tracking.
14.2 Lens Distortion Correction.
14.3 Foveal Sensor.
14.4 Range Imaging.
14.5 Real–Time Produce Grading.
14.6 Summary.
References.
Index.

Nota biograficzna:
Donald G Bailey is Associate Professor in the Institute of Information Sciences and Technology at Massey University, where he leads the Image and Signal Processing Research Group. His research interests include most aspects of image analysis, but in particular the algorithm development process, and training. Bailey has developed a Vision Image Processing System package which has been used in a wide range of image analysis applications. Current and recent projects include: image processing using FPGAs, real time produce grading using machine vision, super–resolution, and sub pixel measurement techniques, camera calibration, and coastal monitoring using automated video analysis. He has been working as an electronics and computer systems engineer in the field of image ana lysis and machine vision for over 25 years. He began applying FPGA technology to image processing in 2002, and since then has published about 25 papers on issues and applications of FPGAs to image processing.

Okładka tylna:
Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine–grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned.Provides a bridge between algorithms and hardwareDemonstrates how to avoid many of the potential pitfallsOffers practical recommendations and solutionsIllustrates several real–world applications and case studiesAllows those with software backgrounds to understand efficient hardware implementation
Design for Embedded Image Processing on FPGAs is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.
The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.
Lecture slides for instructors available at:
www.wiley.com/go/bailey/fpga