FPGA Prototyping by VHDL Examples: Xilinx Spartan–3 Version

A hands–on introduction to VHDL synthesis and FPGA prototyping
Hardware Descriptive Language (HDL) and Field Programmable Gate Array (FPGA) devices
allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. As these technologies have matured, they have become accepted mainstream practice so that it is possible to use a PC and an inexpensive FPGA prototyping board to construct a complex digital system.
This book uses a "learn by doing" approach to introduce the concepts and techniques of VHDL and FPGA to designers through a series of hands–on experiments. FPGA Prototyping by VHDL Examples provides:
A collection of clear, easy–to–follow templates for quick code development
A large number of practical examples to illustrate and reinforce the concepts and design techniques
Realistic projects that can be implemented and tested on a Xilinx prototyping board
A thorough exploration of the Xilinx PicoBlaze soft–core microcontroller
Although the book is an introductory text, the examples are developed in a rigorous manner and the derivations follow strict design guidelines and coding practices used for large, complex systems. It lays a solid foundation for students and new engineers and prepares them for future development tasks. FPGA Prototyping by VHDL Examples is an indispensable companion text for introductory digital design courses and also serves as a valuable self–teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

Spis treści:
Preface.
Acknowledgments.
PART I: BASIC DIGITAL CIRCUITS.
1. Gate–level combinational circuit.
1.1 Introduction.
1.2 General description.
1.2.1 Basic lexical rules.
1.2.2 Library and package.
1.2.3 Entity de claration.
1.2.4 Data type and operators.
1.2.5 Architecture body.
1.2.6 Code of a 2–bit comparator.
1.3 Structural description.
1.4 Testbench.
1.5 Bibliographic notes.
1.6 Suggested experiments.
1.6.1 Code for gate–level greater–than circuit.
1.6.2 Code for gate–level binary decoder.
2. Overview of FPGA and EDA software.
2.1 Introduction.
2.2 FPGA.
2.2.1 Overview of general FPGA device.
2.2.2 Overview of Xilinx Spartan–3 device.
2.3 Overview of Digilent S3 board.
2.4 Design flow.
2.5 Overview of Xilinx ISE project navigator.
2.6 Short tutorial of ISE project navigator.
2.6.1 Create the design project and HDL codes.
2.6.2 Create a testbench and perform RTL simulation.
2.6.3 Add a constraint file and synthesize and implement the code.
2.6.4 Generate and download the configuration file to FPGA devices.
2.7 Short tutorial of ModelSim HDL simulator.
2.8 Bibliographic notes.
2.9 Suggested experiments.
2.9.1 Gate–level greater–than circuit.
2.9.2 Gate–level binary decoder.
3. RT–level combinational circuit.
3.1 Introduction.
3.2 RT–level components.
3.2.1 Relational operators.
3.2.2 Arithmetic operators.
3.2.3 Other synthesis related VHDL constructs.
3.2.4 Summary.
3.3 Routing circuit with concurrent assignment statements.
3.3.1 Conditional signal assignment statement.
3.3.2 Selected signal assignment statement.
3.4 Modeling with process.
3.4.1 Process.
3.4.2 Sequential signal assignment statement.
3.5 Routing circuit with if and case statements.
3.5.1 If statement.
3.5.2 Case statement.
3.5.3 Comparison to concurrent statements.
3.5.4 Unintended memory.
3.6 Constant and generic.
3.6.1 Constant.
3.6.2 Generic.
3.7 Design examples.
3.7.1 Hexadecimal digit to seven–segment LED decoder.
3.7.2 Sign–magnitude adder.
3.7.3 Barrel shifter.< br>3.7.4 A simplified floating–point adder.
3.8 Bibliographic notes.
3.9 Suggested experiments.
3.9.1 Multi–function barrel shifter.
3.9.2 Dual priority encoder.
3.9.3 BCD incrementor.
3.9.4 Floating–point greater–than circuit.
3.9.5 Floating–point and signed integer conversion circuit.
3.9.6 Enhanced floating–point adder.
4. Regular Sequential Circuit.
4.1 Overview.
4.1.1 D FF and register.
4.1.2 Synchronous system.
4.1.3 Code development.
4.2 HDL code of FF and register.
4.2.1 D FF.
4.2.2 Register.
4.2.3 Register File.
4.2.4 Storage components in Spartan–3 deviceXilinx specific.
4.3 Simple design examples.
4.3.1 Shift register.
4.3.2 Binary counter and variant.
4.4 Testbench for sequential circuits.
4.5 Case study.
4.5.1 LED time multiplexing circuit.
4.5.2 Stopwatch.
4.5.3 FIFO buffer.
4.6 Bibliographic notes.
4.7 Suggested experiments.
4.7.1 Programmable square wave generator.
4.7.2 PWM and LED dimmer.
4.7.3 Rotating square circuit.
4.7.4 Heartbeat circuit.
4.7.5 Rotating LED banner circuit.
4.7.6 Enhanced stopwatch.
4.7.7 Stack.
5. FSM.
5.1 Overview.
5.1.1 Mealy and Moore outputs.
5.1.2 FSM representation.
5.2 FSM code development.
5.3 Design examples.
5.3.1 Rising edge detector.
5.3.2 Debouncing circuit.
5.3.3 Testing circuit.
5.4 Bibliographic notes.
5.5 Suggested experiments.
5.5.1 Dual–edge detector.
5.5.2 Alternative debouncing circuit.
5.5.3 Parking lot occupancy counter.
6. FSMD.
6.1 Overview.
6.1.1 Single RT operation.
6.1.2 ASMD chart.
6.1.3 Decision box with register.
6.2 Code development of FSMD.
6.2.1 Debouncing circuit based on RT methodology.
6.2.2 Code with explicit data path components.
6.2.3 Code with implicit data path components.
6.2.4 Comparison.
6.2.5 Testing circuit.
6.3 Design examples.
6.3.1 Fibonacci number circuit.
6.3.2 Division circuit.
6.3.3 Binary–to–BCD conversion circuit.
6.3.4 Period counter.
6.3.5 Accurate low–frequency counter.
6.4 Bibliographic notes.
6.5 Suggested experiments.
6.5.1 Alternative debouncing circuit.
6.5.2 BCD–to–binary conversion circuit.
6.5.3 Fibonacci circuit with BCD I/O: design approach 1.
6.5.4 Fibonacci circuit with BCD I/O: design approach 2.
6.5.5 Auto–scaled low–frequency counter.
6.5.6 Reaction timer.
6.5.7 Babbage difference engine emulation circuit.
PART II: I/O MODULES.
7. UART.
7.1 Overview.
7.2 UART receiving subsystem.
7.2.1 Oversampling procedure.
7.2.2 Baud rate generator.
7.2.3 UART receiver.
7.2.4 Interface circuit.
7.3 UART transmitting subsystem.
7.4 Overall UART system.
7.4.1 Complete UART core.
7.4.2 UART verification configuration.
7.5 Customizing the UART.
7.6 Bibliographic notes.
7.7 Suggested experiments.
7.7.1 Full–featured UART.
7.7.2 A UART with an automatic baud rate detection circuit.
7.7.3 A UART with an automatic baud rate and parity detection circuit.
7.7.4 UART controlled stopwatch.
7.7.5 UART controlled rotating LED banner.
8. PS2 Keyboard.
8.1 Overview.
8.2 PS2 receiving subsystem.
8.2.1 Physical interface of PS2 port.
8.2.2 Device–to–host communication protocol.
8.2.3 Design and code.
8.3 PS2 keyboard scan code.
8.3.1 Overview of scan code.
8.3.2 Scan code monitor circuit.
8.4 PS2 keyboard interface circuit.
8.4.1 Basic design and HDL code.
8.4.2 Verification circuit.
8.5 Bibliographic notes.
8.6 Suggested experiments.
8.6.1 Alternative keyboard interface I.
8.6.2 Alternative keyboard interface II.
8.6.3 PS2 receiving subsystem with watchdog timer.
8.6.4 Keyboard controlled stopwatch.
8.6.5 Keyboard controlled rotating LED banner.
9. PS2 Mo