RapidIO: The Embedded System Interconnect

High–speed, reliable connectivity for next–generation system design
Providing a detailed description of RapidIO applications in several types of system, RapidIO: The Embedded System Interconnect is the first comprehensive reference on the RapidIO interconnect technology. RapidIO was developed specifically to achieve high–performance, low–cost, reliable and scalable system connectivity in embedded, networking, and communications devices. This book presents the motivations for RapidIO and describes how it compares with other interconnect technologies.
Written by one of the founders of the RapidIO Trade Association, this unique resource:Presents an introductory section detailing the history of the RapidIO technologyProvides a practical guide for all of the RapidIO logical layer protocols, network, link and physical layer technologiesDiscusses the usage of RapidIO in embedded systems such as enterprise storage and wireless infrastructureIllustrates newly defined technologies such as the RapidFabric dataplane extensionsDescribes case studies of RapidIO usage in real system architecturesEvaluates the programming models associated with RapidIOReviews related mechanical standards such as the VME Switched Serial Extensions and the PICMG Advanced Telecommunications Architecture (ATCA) standards.
RapidIO: The Embedded System Interconnect is an essential tool for professionals involved in the development of large–scale, high–performance embedded networking, communications and related equipment. With accessible contributions from industry leaders, this book also serves as an excellent reference for common RapidIO packet and symbol formats, register file definitions and system software application programming interfaces.

Spis treści:
Preface.
1 The Interconnect Problem.
1.1 Processor Performance and Bandwidth Growth.
1.2 Multiprocessing.
1.3 System of Systems.
1.4 Problems with Traditional Buses.
1.5 The Market Problem.
1.6 RapidIO: A New Approach.
1.7 Where Will it be Used?
1.8 An Analogy.
References.
2 RapidIO Technology.
2.1 Philosophy.
2.2 The Specification Hierarchy.
2.3 RapidIO Protocol Overview.
2.4 Packet Format.
2.5 Transaction Formats and Types.
2.6 Message Passing.
2.7 Globally Shared Memory.
2.8 Future Extensions.
2.9 Flow Control.
2.10 The Parallel Physical Layer.
2.11 The Serial Physical Layer.
2.12 Link Protocol.
2.13 Maintenance and Error Management.
2.14 Performance.
2.15 Operation Latency.
References.
3 Devices, Switches, Transactions and Operations.
3.1 Processing Element Models.
3.2 I/O Processing Element.
3.3 Switch Processing Element.
3.4 Operations and Transactions.
4 I/O Logical Operations.
4.1 Introduction.
4.2 Request Class Transactions.
4.3 Response Class Transactions.
4.4 A Sample Read Operation.
4.5 Write Operations.
4.6 Streaming Writes.
4.7 Atomic Operations.
4.8 Maintenance Operations.
4.9 Data Alignment.
5 Messaging Operations.
5.1 Introduction.
5.2 Message Transactions.
5.3 Mailbox Structures.
5.4 Outbound Mailbox Structures.
6 System Level Addressing in RapidIO Systems.
6.1 System Topology.
6.2 Switch–based Systems.
6.3 System Packet Routing.
6.4 Field Alignment and Definition.
6.5 Routing Maintenance Packets.
7 The Serial Physical Layer.
7.1 Packets.
7.2 Control Symbols.
7.3 PCS and PMA Layers.
7.4 Using the Serial Physical Layer.
7.5 Transaction and Packet Delivery Ordering Rules.
7.6 Error Detection and Recovery.
7.7 Retimers and Repeaters.
7.8 The Electrical Interface.
8 Parallel Physical Layer Protocol.
8.1 Packet Formats.
8.2 Control Symbol Formats.
8.3 Control Symbol Transmission Alignment.
8.4 Packet Start and Contr ol Symbol Delineation.
8.5 Packet Exchange Protocol.
8.6 Field Placement and Definition.
8.7 Link Maintenance Protocol.
8.8 Packet Termination.
8.9 Packet Pacing.
8.10 Embedded Control Symbols.
8.11 Packet Alignment.
8.12 System Maintenance.
8.13 System Clocking Considerations.
8.14 Board Routing Guidelines.
9 Interoperating with PCI Technologies.
9.1 Address Map Considerations.
9.2 Transaction Flow.
9.3 PCI–X to RapidIO Transaction Flow.
9.4 RapidIO to PCI Transaction Mapping.
9.5 Operation Ordering and Transaction Delivery.
9.6 Interactions with Globally Shared Memory.
9.7 Byte Lane and Byte Enable Usage.
9.8 Error Management.
10 RapidIO Bringup and Initialization Programming.
10.1 Overview of the System Bringup Process.
10.2 System Application Programming Interfaces.
10.3 System Bringup Example.
11 Advanced Features.
11.1 System–level Flow Control.
11.2 Error Management Extensions.
11.3 Memory Coherency Support.
11.4 Multicasting Transactions in RapidIO.
11.5 Multicasting Symbols.
12 Data Streaming Logical Layer (Chuck Hill).
12.1 Introduction.
12.2 Type 9 Packet Format (Data Streaming Class).
12.3 Virtual Streams.
12.4 Configuring Data Streaming Systems.
12.5 Advanced Traffic Management.
12.6 Using Data Streaming.
13 Applications of the RapidIO Interconnect Technology.
13.1 RapidIO in Storage Systems.
13.2 RapidIO in Cellular Wireless Infrastructure (Alan Gatherer and Peter Olanders).
13.3 Fault–tolerant Systems and RapidIO (Victor Menasce).
References.
14 Developing RapidIO Hardware (Richard O’Connor).
14.1 Introduction.
14.2 Implementing a RapidIO End Point.
14.3 Supporting Functions.
14.4 Implementing a RapidIO Switch.
14.5 Summary.
15 Implementation Benefits of the RapidIO Interconnect Technology in FPGAs (Nupur Shah).
15.1 Building the Ecos ystem.
15.2 Advances in FPGA Technology.
15.3 Multiprotocol Support for the Embedded Environment.
15.4 Simple Handshake.
15.5 Low Buffering Overhead.
15.6 Efficient Error Coverage.
15.7 Conclusion.
16 Application of RapidIO to Mechanical Environments (David Wickliff).
16.1 Helpful Features for Mechanical Environments.
16.2 Channel Characteristics.
16.3 Industry Standard Mechanical Platforms Supporting RapidIO.
16.4 Summary.
Appendix A: RapidIO Logical and Transport Layer Registers.
A.1 Reserved Register and Bit Behavior.
A.2 Capability Registers (CARs).
A.3 Command and Status Registers (CSRs).
A.4 Extended Features Data Structure.
Appendix B: Serial Physical Layer Registers.
B.1 Generic End Point Devices.
B.2 Generic End Point Devices: Software–assisted Error Recovery Option.
Appendix C: Parallel Physical Layer Registers.
C.1 Generic End Point Devices.
C.2 Generic End Point Devices: Software–assisted Error Recovery Option.
C.3 Switch Devices.
Appendix D: Error Management Extensions Registers.
D.1 Additions to Existing Registers.
D.2 New Error Management Register.
Index.

Okładka tylna:
High–speed, reliable connectivity for next–generation system design
Providing a detailed description of RapidIO applications in several types of system, RapidIO: The Embedded System Interconnect is the first comprehensive reference on the RapidIO interconnect technology. RapidIO was developed specifically to achieve high–performance, low–cost, reliable and scalable system connectivity in embedded, networking, and communications devices. This book presents the motivations for RapidIO and describes how it compares with other interconnect technologies.
Written by one of the founders of the RapidIO Trade Association, this unique resource:Presents an introductory section detailing the histor