FSM–based Digital Design using Verilog HDL

As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor device is vital. finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic that their alternatives, leading to the development of faster digital hardware systems.
This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital system using FSMs, detailing exactly how and where they can be implemented. with a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and Petri–Net design techniques for sequential/parallel control systems. Chapters on Hardware Description language (HDL) cover the widely–used and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gage and behavioural levels.
throughout, the text incorporates many real–world examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions.
With a linear programmed learning format, this book works as a concise guide for the practising digital designer. this book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.

Spis treści:
CHAPTER 1 – THE BASICS
Introduction
What is a Finite State Machine
Number of States
Number required for State Diagram – Frame 1.3
Mealy FSM
Moore FSM
Class C FSM
Introduction to the State Diagram – State s, Transitions & Inputs
Input Signals – Frames 1.8 to 1.9,
Output Signals – Frame 1.9
Inputs and Outputs of FSM
Inverted Inputs – Frame 1.11
Active High Signals – Frames 1.11
Assignment – Frame 1.11
Non–Unit Distance Coding – Frame 1.11
Secondary State Variables
Unit Distance Coding – Frame 1.12 to Frame 1.14.
Active Low Signals – Frame 1.14
Mealy Outputs – Frame 1.16, 1.19, 1.20, 1.21, from
Effect of clock on Mealy output signals
Summary – Frame 1.22
CHAPTER 2 – CONTROLLING OUTSIDE WORLD DEVICES
Introduction
Using Timer to Introduce Wait States – Frame 2.1 to 2.3
Analogue to Digital Converters – Frame 2.4
Data Acquisition System – Frame 2.4, Frame 2.9 & Frame 2.10 from
Memory:
How to Control in FSM’s – Frame 2.5 to 2.10
Chip Select & Read and Write Sequences
Frames 2.5 to 2.7 – (See also Chapter 4, Section 4.4,
Chapter 5, Sections 5.2, 5.3, 5.4, 5.6, 5.8.)
Monitoring Inputs for Changes – Frame 2.11 to 2.14
Dealing with Incorrect Input States – Frame 2.14
Summary
CHAPTER 3 – SYNTHESISING FSMS
Introduction
Synthesising using T Type Flip Flops – Frame 3.1 to 3.7
T Type Flip Flop
T Flip Flop Example in a State Diagram
Developing T Flip Flop Equations from the State Diagram
Examples of Developing T Equations from a Number of State Diagrams
Solutions to the Examples
D Type Flip Flops
Developing D Flip Flop Equations from a State Diagram
Rule 1: Dealing with 1 to 0 with Input Terms
Rule 2: Dealing with 1 to 1 Transitions
Rule 3: Dealing with two–way Branches
Using the Two–way Branch Rule
Examples of Obtaining D Flip Flop Equations from a State Diagram
State Diagram with Two–way Branch States: Obtaining D Type Equations
Resetting the Flip Flop
Examples of De veloping D Equations from a Number of State Diagrams
Solutions to the Examples
Asynchronous and Synchronous Resetting of Flip Flops
Complete Design of Circuit for a Particular Design
Dealing with Multi–way Branch States using D Type Flip Flops
Dealing with Active Low Output Signals in an FSM
Dealing with Active Low Mealy Output Signals in an FSM
Summary
CHAPTER 4 – SYNCHRONOUS FSM DESIGNS
4.1 Traditional FSM Design Method Verses Method used in this Book
4.2 Dealing with Unused States
4.3 High/Low Alarm Indicator System
4.4 Simple Waveform Generator
4.5 Dice Game
4.6 Binary Data Serial Transmitter
4.7 Development of a Serial Asynchronous Receiver
4.8 Adding Parity Detection to the Serial Receiver System
4.9 Asynchronous Serial Transmitter System
4.10 Clocked Watchdog Timer
4.11 Summary
CHAPTER 5 –ONE HOT DESIGNS
5.1 One Hot Technique of FSM Design
5.2 Data Acquisition System (DAS)
5.3 A Shared Memory System
5.4 Fast Waveform Synthesiser
5.5 Controlling the FSM from a Microprocessor
5.6 Memory Chip Tester
5.7 Comparing One Hot Solution with more Conventional Design
Method of Chapter 4
5.8 Dynamic Memory Access (DMA) Controller
5.9 How to Control the DMA Controller from a Microprocessor
5.10 Detecting Binary Sequences using an FSM
5.11 Summary
CHAPTER 6 – INTRODUCTION TO VERILOG–HDL
A Brief Background to HDLsHardware Modelling with Verilog–HDL – the ModuleModules within Modules : Creating HierarchyVerilog–HDL Simulation : A Complete ExampleReferences and Further Reading
CHAPTER 7 – ELEMENTS OF VERILOG–HDL
Built–in Primitives and Types
7.1.1 Verilog Types
7.1.2 Verilog Logic and Numeric Values
7.1.3 Specifying Values
7.1.4 Verilog–HDL Primitive GatesOperators and ExpressionsExample Illustrating the use of Ver ilog–HDL Operators –
Hamming Code EncoderReferences and Further Reading
CHAPTER 8 – DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG=HDL
The Data Flow Style of Description – Review of the
Continuous AssignmentThe Behavioural Style of Description – The Sequential BlockAssignments within Sequential Blocks : Blocking and
Non–BlockingDescribing Combinational Logic using a Sequential BlockDescribing Sequential Logic using a Sequential BlockDescribing MemoriesDescribing Finite State Machines:
Example 1 Chess Clock Controller FSM
Example 2 Combinational Lock FSM with Automatic
Lock FeatureReferences and Further Reading
CHAPTER 9 – ASYNCHRONOUS FSM DESIGN
9.1 Introduction
9.2 Development of Event Driven Logic
9.3 Using the Sequential Equations to Synthesise an Event FSM
9.3.1 Short Cut Rule
9.4 Implementing the Design using Sum of Product as PLD
9.5 Development of an Event Version of the Single Pulse Generator
with Memory FSM
9.6 Another event FSM design through to simulation
9.7 The Hover Mower FSM
9.8 An Example with a Transition Without any Input
9.9 Unusual Example responding to a Microprocessor
Address Location
9.10 Example that uses a Mealy Output
9.11 Example using a Relay Circuit
9.12 Race Conditions in Event FSMs
9.13 Wait State Generator for a Microprocessor System
9.14 Development of an Asynchronous FSM to Control a Clothes
Spin System
9.15 Summary
CHAPTER 10 – PETRI–NETS
10.1 Introduction to Simple Petri–Nets
10.2 Sequential Petri–Net Example, the Pump Spin Motor Problem
10.3 Parallel Petri–Nets
10.4 Synchronising Flow in a Parallel Petri–Net
10.5 Using Enabling/Disabling Arcs to Synchronise Flow between
Two Petri–Nets
10.6 Example – Control of Shared Resource
10.7 A Serial Receiver