Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn:

Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

Provides extensive treatment of LDPC decoding algorithms and hardware implementationsGives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardwareCompanion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

1. Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. LDPC decoder architectures 6. Hardware implementation of LDPC decoder 7. LDPC decoders in multimedia communication 8. Prospective LDPC applications

Appendix A : Sample C-Programs and MATLAB models for LDPC code construction and simulation B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture