Three-dimensional Integrated Circuit Design

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.

* Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

Chapter 1. Introduction
Chapter 2. Manufacturing of 3-D Packaged Systems
Chapter 3. 3-D Integrated Circuit Fabrication Technologies
Chapter 4. Interconnect Prediction Models
Chapter 5. Physical Design Techniques for 3-D ICs
Chapter 6. Thermal Management Techniques
Chapter 7. Timing Optimization for Two-Terminal Interconnects
Chapter 8. Timing Optimization for Multi-Terminal Interconnects
Appendix A: Enumeration of Gate Pairs in a 3-D IC
Appendix B: Formal Proof of Optimum Single Via Placement
Appendix C: Proof of the Two-Terminal Via Placement Heuristic
Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets
References